According to PredatorZeta:

Just little clarifying.....:)) No. Surely not on 80x86 machines. Look this (is for Pentium):

1 push (mem) take 2 cycles NOT pairable

2 a) mov (mem), reg take 1 cycle pairable AGI Stall (1 cycle+cut off pairing system) b) push reg take 1 cycle pairable

  TOTAL:                    3 cycles

Well, is 2 (not pairable) versus 2 1/2 (not pairable) cycles..... However, with a manual re-ordering it could take only 1 cycle...8-))

Hope this clarify......

Partially. As far as I understand the above, it's

push (mem) 2 cycles not pairable

mov (mem), reg 1 cycle pariable push reg 1 cycle pairable

so both versions have the same speed, but the second one is pairable (-;whatever that means ... I guess it means that it is executed in parallel with a floating point operation, right?). So the second version would be potentially faster, but at least not slower.

It seems that I have missed something ...

Partially confused,

Peter

Dipl.-Phys. Peter Gerwinski, Essen, Germany, free physicist and programmer peter.gerwinski@uni-essen.de - http://home.pages.de/~peter.gerwinski/ [970201] maintainer GNU Pascal [970510] - http://home.pages.de/~gnu-pascal/ [970125]